Arasan and Cadence Collaborate to Extend Verification Best Practices Oct 29, 2009
Oct. 29, 2009 (GLOBE NEWSWIRE) -- Arasan Chip Systems today announced an agreement with Cadence Design Systems to collaborate on delivering functional verification best practices ... According to Cadence, "We see a major trend emerging around SoC integration, leveraging third-party design IP from companies like Arasan. This collaboration simplifies the challenge of verification at the SoC level, and offers a systematic approach to making sure that the protocol design IP can functionally connect... (Primezone Releases)
Cadence shrinks Q3 loss, beats revenue views Oct 29, 2009
SAN FRANCISCO EDA vendor Cadence Design Systems Inc. reported third-quarter sales of $216 million, in line with the company's guidance for the quarter and slightly above consensus analyst estimates for the period. Third-quarter revenue increased 3 percent compared with the second quarter, but was down 7 percent compared to the third quarter of 2008, (San Jose, Calif. (EETimes)
Forum split on future of chip startups Oct 22, 2009
LONDON A discussion panel organized here by Cadence Design Systems Inc. (San Jose, Calif. revealed some of the dynamic tension between the fabless chip startup community and their key suppliers the EDA companies and the foundries. (EETimes)
EDA application runs on iPhone Sep 26, 2009
Sanie has held executive and senior marketing positions at Calypto, Cadence Design Systems, Numerical Technologies and Actel, among others. Sanie said the application was created entirely through homegrown code and graphics. (EETimes)
Verification alive and well at SoC virtual conference Sep 18, 2009
Participants included Brian Bailey, independent consultant; Janick Bergeron, Fellow, Synopsys; Nick Heaton, Senior Architect, Cadence Design Systems and Tom Sandoval, CEO, Calypto Design ... This continuum needs to be closed loop, said Nick Heaton, Senior Architect, Cadence Design Systems: "Too much of the verification methodology is in an open loop and we need to reign it into the design methodology.". (EETimes)
Globalfoundries in multi-year contract with Cadence Sep 1, 2009
MUNICH, Germany Foundry services provider Globalfoundries has signed a multi-year technology contract with semiconductor design software vendor Cadence Design Systems. The deployment covers large parts of the design chain including verification and manufacturing. (EETimes)
RF startup Sequoia Communications shuts down Aug 21, 2009
In addition to Tallwood, other backers of Sequoia included Motorola, Blue Run Ventures, Cadence Design Systems, Gabriel Venture Partners and Hunnington, according to Sequoia's website. A number of startups have been forced to shut their doors over the past several months, hit by the global recession and a dearth of venture capital dollars. (EETimes)
Solving our culture crisis will take more than a shot of innovation Aug 11, 2009
Aart de Geus, chairman and CEO of Synopsys; Walden C. Rhines, chairman and CEO of Mentor Graphics; and Lip-Bu Tan, president and CEO of Cadence Design Systems, were frank in their assessment of their companies, the EDA industry and the tech industry as a whole. "This recession will result in either a giant squeeze or a massive opportunity for EDA companies," said de Geus. (EETimes)
China cranks up fabless startup efforts Aug 8, 2009
Tan is also chief executive of Cadence Design Systems which hopes to provide EDA tools to the new chip companies. The startups, in turn, will serve China's growing ranks of electronics systems companies ranging from HuaWei and ZTE in communications to Lenovo in computers and Konka and TCL in consumer electronics. (EETimes)
Cadence Q2 net hurt by falling sales, charges Jul 31, 2009
Cadence Design Systems Inc.'s second quarter net loss widened sharply on a steep drop in revenue and on higher charges related to ongoing reorganization at the electronic design automation company. Cadence, based in San Jose, Calif. (EETimes)
News from DAC: CEOs debate EDA's fair share Jul 29, 2009
Cadence adds more IP products to Xuropa Online Labs Cadence Design Systems Inc. has increased the number Incisive verification IP products available within Xuropa Online Labs, a cloud-computing application that makes available existing software applications through a software-as-a-service model ... Cadence validates ARM Libraries for 45-nm SOI process Cadence Design Systems Inc. said it has validated a new generation of ASIC libraries from ARM using the Cadence Encounter Digital Implementation... (EETimes)
News from DAC: Magma hit with 'going concern' notice Jul 28, 2009
Cadence validates ARM Libraries for 45-nm SOI process Cadence Design Systems Inc. said it has validated a new generation of ASIC libraries from ARM using the Cadence Encounter Digital Implementation System, targeting IBM's 45-nanometer silicon-on-insulator (SOI) manufacturing process. The ARM 45-nm SOI libraries were developed using the Virtuoso custom design platform 6. (EETimes)
10 companies in trouble Jun 3, 2009
Cadence Design Systems Inc. After being the No. 1 EDA vendor for most of two decades, Cadence hit a rough patch last year and lost its No. 1 standing (along with a lot of money and its management team). The company reported a loss of $1. (EETimes)
Cadence Q1 sales fall further Apr 30, 2009
SAN FRANCISCO EDA vendor Cadence Design Systems Inc. posted a GAAP net loss of $63 million on revenue of $206 million for the first quarter, the company said Wednesday (April 29). Revenue declined 9 percent compared to the previous quarter and 24 percent compared with the same period of 2008. (EETimes)
In the News: Google book probe Apr 29, 2009
-- Bay Area companies expected to report earnings include Akamai Technologies, Bare Escentuals, Cadence Design Systems, Electronics for Imaging, JDS-Uniphase, LSI, Mattson Technology, Openwave Systems, Quantum, Shutterfly, Thomas Weisel Partners, Varian and Visa. This article appeared on page C - 1 of the San Francisco Chronicle. (San Francisco Chronicle -- Business)
Fourth quarter EDA revenue down 18% Apr 8, 2009
Rhines declined to elaborate or even name the vendor, but Cadence Design Systems Inc. is in the midst of transitioning to a more ratable revenue recognition model. Rhines noted that the fourth quarter is traditionally a strong one for EDA. Even though revenue was down nearly 18 percent year-to-year, revenue was up from $1. (EETimes)
EDA startup Pyxis Tech raises $3 million Apr 8, 2009
"The next great battleground in EDA is the custom design arena," said Jim Solomon, Pyxis board member and founder of Cadence Design Systems. "Pyxis NexusRoute-HPC is an OpenAccess-based plug-and-play routing technology that, when coupled with today's leading physical layout editors and placement technology, enables groundbreaking custom design flow productivity.". (EETimes)
Are primary EDA vendors bad? Apr 8, 2009
In recent years, several chip companies have consented to public announcements proclaiming that they have selected a primary vendor first Cadence Design Systems Inc. and, more recently, Synopsys. In a recent interview with EE Times, Rajeev Madhavan, chairman and CEO of Magma Design Automation Inc., criticized the trend and said it is the type of "irresponsible" behavior that has resulted in EDA doing poor job of maintaining adequate pricing for its products. (EETimes)
Video: Where hardware and software collide Apr 4, 2009
Michael MacNamara, a general manager at Cadence Design Systems Inc., said the engineering community forced C to become a general purpose programming language, something it was not necessarily designed for. What the industry needs is a method for capturing the intent of a user and managing priorities, he said. (EETimes)
Design-for-e-beam startup raises $9 million in Series B Apr 3, 2009
The round was led by Benchmark Capital and DAG Ventures, with all prior Series A investors, including Advantest Corp. and Cadence Design Systems Inc. participating. The money is set to be used for market development for the company's design-for-e-beam (DFEB) technology. (EETimes)
Magma CEO upbeat on new products, analog push Mar 28, 2009
Cadence Design Systems Inc. has long been the dominant player in analog design tools. Though Cadence stumbled last year, losing its standing as the No. 1 EDA vendor by revenue, the company's Virtuoso analog franchise is still considered formidable. (EETimes)
LeapFrog Announces Changes to Its Board of Directors Mar 19, 2009
Mr. Simon is President of Lawrence Investments, LLC and has 16 years experience as a partner at Howson & Simon LLP. Mr. Marinelli is Vice President of Lawrence Investments and was previously Corporate Development Group Director at Cadence Design Systems, Inc.. "We would like to thank Steve for his long-term contributions and never-ending passion for the company and Ralph for his dedicated service on our board of directors. We also welcome Philip and Paul to the board and look forward to working... (PR Newswire)
Cadence aims to make power-efficient designs more predictable Mar 17, 2009
Winchester, UK - Cadence Design Systems, Inc., has enhanced the Cadence Low-Power Solution to include support for new on-chip power management schemes enabled by the recently ratified Si2 Common Power Format (CPF) Version 1. 1. (EETimes)
Comment: Cadence back at DAC Mar 13, 2009
Today I received a press release that stated that Cadence design Systems will be the sole sponsor of both the User Track and Management DAY at the upcoming 46th DAC. In addition Cadence will have a presence on the Exhibit floor in the new IC Design Chain booth and with the booth of Chipestimate, which is a part of Cadence. This is good news for the vast majority of people in the EDA industry since it is a sign that Cadence is once again ready to take an active role to promote the industry. (EETimes)
Lithography hit by R&D gap, downturn Mar 5, 2009
Based on the troubling trends, NGL needs more funding or a large ''stimulus package,'' warned Milind Weling, engineering director of signoff and silicon optimization for Cadence Design Systems Inc.. Some technologies like EUV remain delayed or on the ropes, leaving leading-edge chip makers to resort to an assortment of complex, costly and unpopular double-patterning schemes. (EETimes)
SPIE panel: EUV on the ropes Feb 27, 2009
This year, it's more of a question of 'if,' '' said Milind Weling, engineering director of signoff and silicon optimization for Cadence Design Systems Inc. (San Jose), during the panel, which was sponsored by Applied Materials Inc. (Santa Clara, Calif. . (EETimes)
What is source-mask optimization? Feb 27, 2009
A number of companies are either developing or offering for sale SMO tools, including IBM, Brion Technologies, Luminescent Technologies Inc., Nikon Corp. and Cadence Design Systems Inc.. But Ferrell and an executive from Mentor Graphics Corp., which is working with IBM on SMO for computational scaling, say the work being done by other firms does not truly optimize the mask, instead focusing on optimization of the illumination source for use with a reticle incorporating standard optical proximity... (EETimes)
Layout optimization startup Tela buys Blaze DFM Feb 25, 2009
Tela, founded in 2005, is privately funded by several venture capital firms and boasts former Cadence Design Systems Inc. executives Ray Bingham and Jim Hogan on its board of directors. Page 2. (EETimes)
Will Synopsys rule the world? Feb 21, 2009
By contrast, Cadence Design Systems Inc. reported a GAAP net loss of $1. 85 billion for fiscal 2008 and expects revenue to be down significantly this year. (EETimes)
Cadence reports $1.64 billion Q4 loss Feb 7, 2009
SAN FRANCISCO Dragged down by a huge non-cash impairment charge related to the write down on goodwill, beleaguered EDA vendor Cadence Design Systems Inc. Wednesday (Feb. 4) reported a net loss of $1. (EETimes)
